RISC-V

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Figura 1: Logomarca [3]

Figura 2: registradores [2]

.global _start

_start:

# STDOUT FD = 1

addi a7, zero, 64

addi a0, zero, 1

la al, olamundo

addi a2, zero, 13

ecall

addi a7, zero, 93

addi a0, zero, 13

ecall

olamundo:

.ascii "olá mundo\n"

----- Código exemplo [2] -----

Figura 3: Versões [4]

RV32I Base Integer Instruction Set, Version 2.1

RV64I Base Integer Instruction Set, Version 2.1

RV128I Base Integer Instruction Set, Version 1.7

"M” Standard Extension for Integer Multiplication and Division, Version 2.0

"A” Standard Extension for Atomic Instructions, Version 2.1

"F” Standard Extension for Single-Precision Floating-Point, Version 2.2

"D” Standard Extension for Double-Precision Floating-Point, Version 2.2

"Q” Standard Extension for Quad-Precision Floating-Point, Version 2.2

"L” Standard Extension for Decimal Floating-Point, Version 0.0

"C” Standard Extension for Compressed Instructions, Version 2.0

"B” Standard Extension for Bit Manipulation, Version 0.0

"J” Standard Extension for Dynamically Translated Languages, Version 0.0

"T” Standard Extension for Transactional Memory, Version 0.0

"P” Standard Extension for Packed-SIMD Instructions, Version 0.2

"V” Standard Extension for Vector Operations, Version 0.7

"Zam” Standard Extension for Misaligned Atomics, v0.1

"Ztso” Standard Extension for Total Store Ordering, v0.1

Figura 4: Registradores [4]

instruction-set architecture (ISA)

execution environment interface (EEI)

application binary interface (ABI)

supervisor binary interface (SBI)

Weak Memory Ordering (RVWMO) Ordenação de Memória Fraca

Four core instruction formats (R/I/S/U)

Referência:

1] http://www2.decom.ufop.br/imobilis/o-risc-v/

2] https://www.youtube.com/watch?v=GWiAQs4-UQ0

3] https://riscv.org/

4] riscv/riscv-spec-20191213.pdf

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